1. Field of the Invention
The present invention relates to an emitter coupled logic (ECL) to complementary metal oxide semiconductor (CMOS) translator, and more particularly, to an improved high speed, ECL to CMOS translator which uses a dynamic internally generated reference potential.
2. Description of the Prior Art
With the advent of BiCMOS technology, which combines the advantages of both bipolar and CMOS technologies on a single semiconductor integrated circuit (IC), ECL to CMOS translators are required to translate signals from ECL logic levels to CMOS logic levels. For example, an ECL to CMOS translator may be used to translate complementary signals at ECL logic levels to complementary signals at corresponding CMOS logic levels.
ECL circuits operate between a four and half to a five volt differential and have a logic swing ranging from (-0.8) volts below the upper potential to 2.0 volts above the lower potential. For example, if the voltage differential is set from (-4.5) volts to (0.0) volts, a signal having a potential ranging from (-0.8) volts to (0.0) volts is a logical high, and a signal having a potential ranging from (-4.5) to (-1.6) volts is a logical low.
CMOS circuits also operate between a four and a half to a five volt differential and have a logic swing ranging from 1.5 volts below the upper potential and 1.5 volts above the lower potential. For example, if the voltage differential is set from (-4.5) to (0.0), a signal having a potential ranging from (-1.5) to (0.0) volts is a logical high, and a signal having a potential ranging from (-4.5) to (-3.0) is a logical low.
Referring to FIG. 1, a known ECL to CMOS translator circuit according to the prior art is shown. Translator 10 includes input circuit 12, a reset circuit 14, and complementary output circuits 16 and 17. The translator 10 is coupled between ECL logic circuit 18 and CMOS logic circuit 20.
Two emitter-follower transistors 26 and 28 are used to supply the complementary ECL output signals from ECL circuit 18 to nodes B and A respectively at the input of input circuit 12. The first emitter-follower transistor 26 has its base coupled to ECL circuit output node 24, its collector coupled to V.sub.cc, and its emitter coupled to node B. The second emitter-follower transistor 28 has its base coupled to ECL circuit output 22, its collector coupled to V.sub.cc, and its emitter coupled to node A. V.sub.cc equals the highest supply voltage of the circuit, which in this example, equals (0.0) volts.
Translation input circuit 12 includes a first enhancement P channel transistor M1 and a second enhancement P channel transistor M2. Transistor M1 has its source (S) coupled to node A, and its drain (D) coupled to node C. Transistor M2 has its source (S) coupled to node B, and its drain (D) coupled to node D. The gates of transistors M1 and M2 are coupled to the common voltage reference V.sub.ref generated by external voltage reference circuit 30.
Reset circuit 14 includes a first N channel enhancement transistor M3, a second N channel enhancement transistor M4, a third N channel enhancement transistor M5 and a fourth N channel enhancement transistor M6. M3 has its drain (D) coupled to node C, its gate coupled to node B, and its source (S) coupled to node E. M4 has its drain (D) coupled to node D, its gate coupled to node A, and its source (S) coupled to node F. M5 has its drain (D) coupled to node E, its gate coupled to node D, and its source (S) coupled to ground. M6 has its drain (D) coupled to node E, its gate coupled to node D, and its source (S) connected to ground.
Output circuits 16 and 17 are well known CMOS inverters operating between the CMOS logic range of V.sub.cc and ground. Output circuit 16 includes a P channel enhancement transistor M7 and an N channel enhancement transistor M8. Transistor M7 has its source (S) coupled to V.sub.cc, its gate coupled to node C, and its drain coupled to V.sub.out. Transistor M8 has its drain (D) coupled to V.sub.out, its gate coupled to node C and its source (S) coupled to ground. Output circuit 17 includes a P channel enhancement transistor M22 and an N channel enhancement transistor M23 arranged in the identical manner as output translation circuit 16.
Referring to FIG. 2, a timing diagram illustrating the ECL to CMOS translation operation of the circuit shown in FIG. 1 is shown. The diagram is divided into three sections. In the first section (I), the switching operation of the ECL nodes A and B between (0.8 to -2.0) volts is shown. In the second section (II), the switching operation of nodes C and D between (-1.0 and -4.5) volts is shown. In section (III), the switching operation between the full CMOS logic range of (-4.5 to 0.0) volts at Vout and [Vout] is shown.
During operation of translator 10, ECL logic circuit 18 generates complementary ECL signals at nodes 22 and 2 respectively. The ECL signals are used to drive emitter-follower-transistors 26 and 28, which in turn are used to provide low impedance ECL level signals at nodes B and A respectively. For example, if a high ECL signal is presented at node 24, emitter-follower transistor 26 generates a high ECL signal at its emitter and node B is pulled up to A VOH of -VBE (-0.8 volts) The complementary low ECL signal at node 22 drives emitter-follower transistor 28 and node A to A VOL (-2.0 volts) as determined by the gain of the ECL device. The voltage at node A is equal to the voltage at node 22 minus the base-emitter voltage drop of transistor 28. Since ECL logic circuit 18 is approximately (-1.2 volts) and the V.sub.BE of transistor 28 is approximately (-0.8 volts).
Conversely, if node 22 is at a high ECL level and node 24 is at a low ECL level, emitter follower transistors 28 and 26 operate to pull node A up to V.sub.OH of V.sub.BE (-0.8 volts) and node B remains low at (-2.0 volts). The two emitter-follower transistors 26 and 28 dissipate current, as illustrated by the current sources S1, and S2, coupled to the emitters of transistors 26 and 28 respectively.
Translation input circuit 12 is responsible for receiving the complementary ECL signals at nodes A and B, and comparing the potential of the two signals with reference of voltage V.sub.ref, which is set to a voltage near the middle of the operating range of nodes A and B. Based on the comparison, transistors M1 and M2 are used to control the potential at complementary nodes C and D respectively. Nodes C and D operate at two discrete states, V.sub.AAH (-1.0 volts) and V.sub.AAL (-4.5 volts). The potential of V.sub.AAH is intermediate the full CMOS level.
In the event that the potential at node A is higher than V.sub.ref plus a gate threshold (V.sub.T), transistor M1 is turned on, and node C is pulled up to V.sub.AAH. Conversely, in the event the potential at node A is less than V.sub.ref, transistor M1 is turned off. Similarly, in the event the potential at node B is greater than V.sub.ref plus (V.sub.T), transistor M2 is turned on and pulls up node D to V.sub.AAH. In the event the potential signal at node B is less than V.sub.ref, transistor M2 is turned off
Reset circuit 14 is responsible for monitoring the complementary signals presented at nodes C and D, and adjusting potential of nodes C and D as transistors M1 and M2 respectively turn on. For example, in the event transistor M1 is turned on, reset circuit 14 operates to pull down node D to V.sub.AAL. With nodes B and D at low potentials and coupled to the gates of transistors M3 and M5 respectively, transistors M3 and M5 turn off and node C is pulled up by M1 to V.sub.AAH. In the event transistor M2 is turned off, transistors M3, M4, M5 and M6 operate in the complement to that described above to reset or pull up node D to V.sub.AAH.
Output translation circuits 16 and 17 are responsible for receiving the intermediate level (V.sub.AAH and V.sub.AAL) complementary potential signals at nodes C and D respectively, and translating them into complementary signals in the full CMOS logic range.
During operation of translation circuit 16, in the event node C is low at V.sub.AAL, transistor M7 is turned on and transistor M8 is turned off. As a result, V.sub.out equals V.sub.cc. In the event node C is high, transistor M7 is turned off and transistor M8 is turned on, and as a result, V.sub.out equals V.sub.ss. Output translation circuit 17 operates in the identical manner to produce CMOS output level signals at [V.sub.out ] as node D switches between V.sub.AAH and V.sub.AAL.
The prior art ECL to CMOS translator as described above has a number of deficiencies. First, the generation of V.sub.ref requires that a specific circuit, separate from the circuit of translator 10, be designed, laid out and fabricated on the die containing translation circuit 10. The addition of external reference circuit 30 therefore decreases the die surface area available for other circuitry. Reference circuit 30 also increases the number and complexity of processing steps required to fabricate the die, which may significantly decrease the manufacturing yield of a BiCMOS IC containing the prior art ECL to CMOS translator 10.
Another problem associated with prior art translator 10 is the time required for ECL to CMOS translation. Translator 10, with its input, reset and output stages 12, 14, 16 and 17, requires numerous gate delays to complete the ECL to CMOS translation. Generally, the translation time for ECL to CMOS translator 10 of the prior art ranges approximately from 700 to 800 pico-seconds, which is relatively slow for many of today's high speed BiCMOS products.
The reference voltage V.sub.ref also is responsible for slowing down the translation speed of translator 10. Since V.sub.ref is set at approximately in the middle of the CMOS operating range, transistors M1 and M2 require a longer period of time to turn on and off in response to a change of potential at nodes A and B respectively.
Another problem of prior art ECL to CMOS translator 10 is the lack of utilization of the current dissipated by current sources S1 and S2 of emitter-follower transistors 26 and 28.